1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and its test method, and more specifically to a semiconductor integrated circuit device provided with both a counter circuit and a test circuit and its test method.
2. Description of the Prior Art
FIG. 12 is a circuit diagram showing an example of the prior art semiconductor integrated circuit device having a counter circuit 30. The counter circuit 30 is composed of (n+3)-stage flip-flops. Further, a test circuit 40 composed of three inverters 40a to 40c is connected between the (n+1)-stage flip-flop and the (n+2)-stage flip-flop. In these three inverters, the two inverters 40a and 40b are those which can be switched (i.e., turned on or off) on the basis of two control signals TEST and /TEST, and the remaining inverter 40b is an ordinary inverter. In other words, this test circuit 40 is provided with such a function as to switch the semiconductor integrated circuit device from an ordinary operation mode to a test mode or vice versa, by turning the two inverters 40a and 40c on or off in response to the two control signals TEST and /TEST, respectively.
The operation of the prior art semiconductor integrated circuit device shown in FIG. 12 will be described hereinbelow.
In the ordinary operation mode in which the control signal is /TEST, the inverter 40a is turned on and the inverter 40c is turned off. Therefore, the (n+1)-stage flip-flop and the (n+2)-stage flip-flop are substantially connected to each other through the two inverters 40a and 40b of the test circuit 40. Therefore, an input count clock CK is inputted to the first stage flip-flop (on the left side in FIG. 12) of the counter circuit 30a, and a signal is outputted from the (n+3)-stage flip-flop (on the right side in FIG. 12) of the counter circuit 30b. In other words, the semiconductor integrated circuit device functions as a counter circuit having the (n+3)-stage flip-flops as a whole.
On the other hand, in the operation test mode in which the control signal is TEST, the inverter 40a is turned off and the inverter 40c is turned on. Therefore, the inputted count clock signal CK is directly inputted to the (n+2)-stage flip-flop connected midway of the counter circuit 30 through the two inverters 40c and 40b of the test circuit 40. That is, the inputted count clock CK is inputted to a first half counter circuit 30a and further to a second half counter circuit 30b. In this case, however, since the inverter 40a is kept turned off, the signal outputted by the (n+1)-stage flip-flop of the first counter circuit 30a is stopped, so that it is impossible to decide whether the counter circuit operates normally or not. On the other hand, the signal outputted from the (n+3)-stage flip-flop of the second counter circuit 30b is received by various circuits (not shown) connected on the output side of the second counter circuit 30b. Therefore, it is possible to check whether the operation of the counter circuit 30 is normal or not on the basis of a predetermined signal outputted by the counter circuit 30 and by use of a detecting circuit of these various circuits.
In the semiconductor integrated circuit device as shown in FIG. 12, since the operation test of the counter circuit 30 can be made as described above, it is possible to shorten the time required for the operation test of the circuit device.
FIG. 13 is a circuit diagram showing another prior art semiconductor integrated circuit device having a counter circuit 32, which is disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 63-186167. The counter circuit 32 is composed of 8-stage flip-flops; in more detail, the counter circuit 32 is composed of a first counter circuit 32a including first half four-stage flip-flops and a second half counter circuit 32b including second half four-stage flip-flops. Here, the first counter circuit 32a and the second counter circuit 32b of the counter circuit 32 are divided by use of a dividing circuit 42b of a test circuit 42. The test circuit 42 is provided with such a function as to switch the ordinary operation mode to the operation test mode or vice versa.
The operation of the semiconductor integrated circuit device shown in FIG. 13 will be described hereinbelow. In the ordinary operation mode, the first half counter circuit 32a and the second half counter circuit 32b are connected to each other through the dividing circuit 42b. Therefore, an input count clock CK is applied to the first half counter circuit 32a and then derived from the second half counter circuit 32b. In other words, this semiconductor integrated circuit device can function as the counter circuit 32 having 8-stage flip-flops as a whole.
On the other hand, in the operation test mode, the counter circuit 32 is divided into the first half counter circuit 32a and the second half counter circuit 32b. Further, the input count clock CK is inputted to both the first and second counter circuits 32a and 32b at the same time. Here, each output of each flip-flop of the first and second counter circuits 32a and 32b is compared with a correct truth value for each clock by a comparison circuit 42a. These correct truth values are inputted through terminals CD1 to CD4 shown on the left side in FIG. 13. Therefore, it is possible to check whether the counter circuit 32 operates normally by checking whether all the outputs of all the flip-flops match the correct truth values, respectively.
In the semiconductor integrated circuit device as shown in FIG. 13, since the operation test of the counter circuit 32 can be made as described above, it is possible to shorten the time required for the operation test of the circuit device.
In the semiconductor integrated circuit device shown in FIG. 12, however, all the flip-flops of the counter circuit 30 are not activated in the operation test. In more detail, although the flip-flops for constituting the second half counter circuit 30b are all activated, the flip-flops for constituting the first half counter circuit 30b are not at all activated, so that the circuit activation ratio of the counter circuit 30 itself is relatively low. Therefore, in case any of the flip-flops for constituting the first half counter circuit 30a is defective, the defective flip-flop cannot be checked.
On the other hand, in the semiconductor integrated circuit device shown in FIG. 13, since all the flip-flops are activated, the circuit activation ratio is high. In the operation test mode, however, since each output of each flip-flop must be compared with each correct truth value for each input count clock CK by use of the comparison circuit 42a, a relatively large-scale comparison circuit 42a is required and thereby the circuit scale of the whole semiconductor integrated circuit device inevitably increases, thus resulting in a problem in that the device cost increases as a whole. In addition, since the terminals CD1 to CD4 must be provided for the circuit device to input the correct truth values from the outside, the number of steps for manufacturing the terminals increases.